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Novel Low-Resistance Current Path UMOS With High-K Dielectric Pillars

机译:具有高K介电支柱的新型低电阻电流路径UMOS

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A low specific on-resistance $(R_{rm on,sp})$ UMOS with high permittivity (HK) dielectric pillars underneath the p body region (HK UMOS) is proposed and investigated. Its drift region uniquely consists of two narrow and highly-doped n pillars and one lightly doped ${rm n}^{-}$ pillar, which is parallel to the HK dielectric pillars. First, the highly-doped n pillars offer low resistance current paths in the ON-state while the ${rm n}^{-}$ region sustains high voltage in the OFF-state. Second, the HK dielectric causes an enhanced self-adapted lateral assistant depletion of the n pillars, which allows to keep a higher doping concentration of the n pillars and thus further reduces the $R_{rm on,sp}$. Third, the HK dielectric enhances the vertical field strength in high-voltage blocking state, leading to an improved breakdown voltage (BV). Compared with a conventional UMOS at the highest figure-of-merit, the HK UMOS with $k_{D}=200$ not only decreases the $R_{rm on,sp}$ by 67%, but also increases the BV by 12%.
机译:具有高介电常数(HK)介电柱的UMOS低比导通电阻 $(R_ {rm on,sp})$ 在p体区域(HK UMOS)下面提出并进行了研究。其漂移区独特地由两个窄且高度掺杂的n柱和一个轻度掺杂的 $ {rm n} ^ {-} $ 支柱,它平行于HK介电支柱。首先,高掺杂n柱在导通状态下提供低电阻电流路径,而 $ {rm n} ^ {-} $ 区域在OFF状态下维持高压。其次,HK介电质会增强n根支柱的自适应横向辅助损耗,从而可以保持n根支柱的较高掺杂浓度,从而进一步降低 $ R_ {rm on,sp} $ 。第三,HK电介质增强了高压阻断状态下的垂直场强度,从而提高了击穿电压(BV)。与具有最高品质因数的传统UMOS相比,具有 $ k_ {D} = 200 $ 的香港UMOS不仅可以将 $ R_ {rm on,sp} $ 降低67%,而且BV可以提高12%。

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