Analytical Gate Capacitance Modeling of III–V Nanowire Transistors

摘要

In this paper, we propose a physically based analytical model for the gate capacitance $(C_{rm G})$ of III–V nanowire (NW) transistors. The model explicitly accounts for different terms that contribute to $C_{rm G}$: the insulator capacitance, the finite density of states, and the charge distribution in the NW. It considers the 2-D quantum confinement of the carriers, the wavefunction penetration into the gate insulator, Fermi-Dirac statistics and the conduction band nonparabolicity, providing analytical expressions for all the capacitance contributions. Furthermore, the behavior and role of the density of states and the charge distribution in the NW are discussed for several materials and the influence of the wavefunction penetration into the gate insulator is also studied. We show that our analytical model is in very good agreement with the numerical solution for different device sizes and materials.