High-Mobility Ge p- and n-MOSFETs With 0.7-nm EOT Using src='/images/tex/20780.gif' alt='hbox {HfO}_{2}/hbox {Al}_{2}hbox {O}_{3}/hbox {GeO}_{x}/hbox {Ge}'> Gate Stacks Fabricated by Plasma Postoxidation

摘要

An ultrathin equivalent oxide thickness (EOT) $hbox{HfO}_{2}/hbox{Al}_{2} hbox{O}_{3}/hbox{Ge}$ gate stack has been fabricated by combining the plasma postoxidation method with a 0.2-nm-thick $hbox{Al}_{2}hbox{O}_{3}$ layer between $hbox{HfO}_{2}$ and Ge for suppressing $hbox{HfO}_{2}{-}hbox{GeO}_{x}$ intermixing, resulting in a low-interface-state-density $(D_{rm it})$  $hbox{GeO}_{x}/hbox{Ge}$ metal–oxide–semiconductor (MOS) interface. The EOT of these gate stacks has been scaled down to 0.7–0.8 nm with maintaining the $D_{rm it}$ in $ hbox{10}^{11} hbox{cm}^{-2}cdot hbox{eV}^{-1}$ level. The p- and n-channel MOS field-effect transistors (MOSFETs) (p- and n-MOSFETs) using this gate stack have been fabricated on (100) Ge substrates and exhibit high hole and electron mobilities. It is found that the Ge p- and n-MOSFETs exhibit peak hole mobilities of 596 and 546 $hbox{cm}^{2}/hbox{V}cdot hbox{s}$ and peak electron mobilities of 754 and 689 $hbox{cm}^{2}/hbox{V}cdot hbox{s}$ at EOTs of 0.82 and 0.76 nm, respectively, which are the record-high reports so far for Ge MOSFETs in subnanometer EOT range because of the sufficiently passivated Ge MOS interfaces in present $hbox{HfO}_{2}/hbox{Al}_{2}hbox{O}_{3}/hbox{- eO}_{x}/hbox{Ge}$ gate stacks.