Pixel Design Driven Performance Improvement in 4T CMOS Image Sensors: Dark Current Reduction and Full-Well Enhancement

摘要

Dark current (DC) limits the optical performance of CMOS image sensors. The main sources of the DC in a modern submicrometer process are the defects induced by the shallow trench isolation fabrication process steps. In this brief, we present a pixel layout technique to reduce the impact of these defects by removing the trench-oxide between the two adjacent edges of neighboring photodiodes (PDs). This isolation scheme relies only on the p-well layer and provides the further advantage of requiring less area. Hence, a larger PD can be designed, leading to an increased pixel fill factor. Experimental results show that this approach reduces the DC by 21 and increases the linear full well capacity by approximately 9.