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Thorough Understanding of Retention Time of Z2FET Memory Operation

机译:彻底了解Z2FET存储器操作的保留时间

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摘要

A recently reported zero impact ionization and zero subthreshold swing device Z2FET is a promising candidate for capacitor-less dynamic random access memory (DRAM) memory cell. In the memory operation, data retention time determines refresh frequency and is one of the most important memory merits. In this paper, we have systematically investigated the Z2FET retention time based on a newly proposed characterization methodology. It is found that the degradation of HOLD “0” retention time originates from the gated-silicon on insulator (SOI) portion rather than the intrinsic-SOI region of the Z2FET. Electrons accumulate under front gate and finally collapse the potential barrier turning logic “0”–“1.” It appears that Shockley–Read–Hall (SRH) generation is the main source for electrons accumulation. Z2FET scalability has been investigated in terms of retention time. As the Z2FET is downscaled, the mechanism dominating electrons accumulation switches from SRH to parasitic injection of electrons from the cathode. The results show that the downscaling of Lg has little effect on data “0” retention, but Lin is limited to ~125 nm. An optimization method of the fabrication process is proposed based on this new understanding, and Lin can be further scaled down to 75 nm. We have demonstrated by 2-D TCAD simulation that Z2FET is a promising DRAM cells’ candidate particularly for Internet-of-Things applications.
机译:最近报道的零冲击电离和零亚阈值摆动器件Z2FET是无电容器动态随机存取存储器(DRAM)存储单元的有希望的候选者。在存储操作中,数据保留时间决定刷新频率,并且是最重要的存储优点之一。在本文中,我们基于一种新提出的表征方法,系统地研究了Z2FET的保留时间。发现HOLD“ 0”保留时间的下降源自绝缘体上的栅化硅(SOI)部分,而不是Z2FET的本征SOI区域。电子积聚在前栅极之下,最终使势垒转向逻辑“ 0”至“ 1”崩溃。似乎肖克利-雷德-霍尔(SRH)的产生是电子积累的主要来源。 Z2FET可扩展性已根据保留时间进行了研究。随着Z2FET的尺寸缩小,控制电子积累的机理从SRH切换为从阴极寄生注入电子。结果表明,Lg的缩小对数据“ 0”的保留几乎没有影响,但Lin被限制在〜125 nm。基于这一新的认识,提出了一种制造工艺的优化方法,Lin可以进一步缩小至75 nm。通过2D TCAD仿真,我们已经证明Z2FET是有前途的DRAM单元的候选产品,特别是在物联网应用中。

著录项

  • 来源
    《Electron Devices, IEEE Transactions on》 |2019年第1期|383-388|共6页
  • 作者单位

    School of Engineering, University of Glasgow, Glasgow, U.K.;

    Department of Electronics and Computer Technology, University of Granada, Granada, Spain;

    Synopsys Glasgow, Glasgow, U.K.;

    School of Engineering, University of Glasgow, Glasgow, U.K.;

    School of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan, China;

    School of Engineering, University of Glasgow, Glasgow, U.K.;

    Department of Electronics and Computer Technology, University of Granada, Granada, Spain;

    Department of Electronics and Computer Technology, University of Granada, Granada, Spain;

    School of Engineering, University of Glasgow, Glasgow, U.K.;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    Logic gates; Random access memory; Electric potential; Degradation; Cathodes; Electron traps;

    机译:逻辑门;随机存取存储器;电势;退化;阴极;电子陷阱;

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