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首页> 外文期刊>IEEE Electron Device Letters >Stability of N-channel polysilicon thin-film transistors with ECR plasma thermal gate oxide
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Stability of N-channel polysilicon thin-film transistors with ECR plasma thermal gate oxide

机译:具有ECR等离子体热栅氧化物的N沟道多晶硅薄膜晶体管的稳定性

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摘要

The effects of electrical stress on n-channel polysilicon thin-film transistors (poly-Si TFTs) with electron cyclotron resonance (ECR) plasma gate oxide have been investigated. The plasma-hydrogenerated low-temperature (/spl les/600/spl deg/C) TFT's exhibited very a small increase of threshold voltage (/spl Delta/V/sub th/>0.3 V) under the stress conditions (V/sub gs/=15 V, V/sub ds/=0 V /spl sim/15 V, and stress time=5/spl times/10/sup 4/ s). The /spl Delta/V/sub t/h was larger for the stress in the linear region than in the saturation region. It was found that the device degradation for the stress in the saturation region was caused by the hot-carriers. Increase of OFF current was maximum for the stress at V/sub gs/=V/sub ds/ while for the stress at V/sub gs/>V/sub ds/, degradation of transconductance was the dominant effect seen.
机译:研究了电应力对具有电子回旋共振(ECR)等离子栅氧化物的n沟道多晶硅薄膜晶体管(poly-Si TFT)的影响。等离子体产生的低温(/ spl les / 600 / spl deg / C)TFT在应力条件(V / sub)下阈值电压(/ spl Delta / V / sub th /> 0.3 V)的增加很小gs / = 15 V,V / sub ds / = 0 V / spl sim / 15 V,应力时间= 5 / spl次/ 10 / sup 4 / s)。对于线性区域中的应力,/ spl Delta / V / sub t / h大于饱和区域中的应力。已经发现,由于热载流子引起的饱和区应力的器件劣化。对于V / sub gs / = V / sub ds /处的应力,OFF电流的增加最大,而对于V / sub gs / V / sub ds /下的应力,跨导的降低是主要的影响。

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