Gate-induced drain-leakage in buried-channel PMOS-a limiting factor in development of low-cost, high-performance 3.3-V, 0.25-/spl mu/m technology

摘要

This paper presents a low cost 0.25-/spl mu/m technology with low standby power for 3.3 V applications. It is shown that as a single gate oxide n-type polysilicon gate technology is scaled, gate-induced drain-leakage (GIDL) in buried-channel PMOS becomes a serious limiting factor in achieving low standby power. The impact of technology choices such as spacer material, spacer width and poly reoxidation conditions on PMOS GIDL is discussed. A technology that successfully limits PMOS leakage is presented.