1000-V 9.1-$hbox{m}Omega cdot hbox{cm}^{2}$ Normally Off 4H-SiC Lateral RESURF JFET for Power Integrated Circuit Applications

摘要

A 4H-SiC normally off vertical channel lateral reduced-surface electric-field (RESURF) junction field-effect transistor (JFET) with a blocking voltage $V_{rm br}$ of 1028 V and a specific on-resistance $R_{{rm on}hbox{-}{rm sp}}$ of 9.1 $hbox{m}Omega cdot hbox{cm}^{2}$ has been experimentally demonstrated. The device has a $V_{rm br}^{2}/R_{{rm on}hbox{-}{rm sp}}$ figure-of-merit of 116 $hbox{MW/cm}^{2}$, which is the highest value achieved to date on a 4H-SiC lateral power transistor. Also reported is a larger JFET that is capable of handling over 0.5-A current on an active area of $hbox{4.01} times hbox{10}^{-3} hbox{cm}^{2}$. The fabricated double-RESURF devices have a vertical channel length of 1.8 $muhbox{m}$, created by tilted aluminum (Al) implantation on the sidewalls of deep trenches, and a lateral drift-region length of 7.5 $muhbox{m}$. In addition, low-voltage logic-inverter circuits based on the same lateral JFET process have been monolithically integrated on the same chip. Proper logic-inverter function has also been demonstrated.