Data-plane-processor IP quadruples data bandwidth, doubles instruction size to 128 bits

摘要

Tensilica's new Xtensa LX4 DPU (data-plane processor) for SOCs (systems on chips) has four times more local data-memory bandwidth than the previous-generation LX3 DPU. The LX4 supports as many as two 512-bit load/store operations per cycle and doubles VLIW (very-long-instruction-word) instruction width from 64 bits to 128 bits for increased parallel processing. By applying the cache-memory-prefetch feature in the LX4, you can increase performance in systems with long off-chip latency by fetching data from system memory before its use.