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Die size does not determine IC cost

机译:芯片尺寸不决定IC成本

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Years ago, you could look at the size of a semiconductor die and make a good guess about the manufacturer's cost. This situation is no longer true, even if you understand that a fine-line CMOS process costs more than a 250-nm process and CMOS processes tend to cost less than bipolar or BiCMOS processes (Reference 1). Even if you know the cost of a chip's process, you still have no idea of the required test time—an important factor because test time is a major component of an IC's cost. Bob Reay, vice president and general manager of mixed-signal products at Linear Technology, points out that the company fabricates ADC chips with a ring of thick metallization around the periphery of the die. Linear runs large currents through this ring at test time.
机译:几年前,您可以研究一下半导体芯片的尺寸,并对制造商的成本做出很好的猜测。即使您了解细线CMOS工艺的成本比250-nm工艺高,而CMOS工艺的成本往往低于双极或BiCMOS工艺,这种情况已不再成立(参考文献1)。即使您知道芯片处理的成本,也仍然不知道所需的测试时间,这是一个重要因素,因为测试时间是IC成本的主要组成部分。凌力尔特公司(Linear Technology)副总裁兼混合信号产品总经理Bob Reay指出,该公司制造的ADC芯片在芯片的外围带有一层厚金属化的环。线性在测试时通过该环流过大电流。

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