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A discrete phase-locked loop for undergraduate laboratories

机译:大学实验室的离散锁相环

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摘要

Phase-locked loop (PLL) experiments in undergraduate instructional laboratories are usually designed around a monolithic IC chip. However, insight into circuit operation is mostly lost with use of the IC chip. In this paper, a PLL circuit consisting of only three transistors is presented. Given its simple topology, it can be realized with discrete components and requires minimal analysis. Hence, the presented circuit is ideally suited for demonstrating PLL principles in undergraduate laboratories.
机译:本科教学实验室中的锁相环(PLL)实验通常是围绕单片IC芯片设计的。然而,由于使用IC芯片,大部分失去了对电路操作的了解。本文提出了仅由三个晶体管组成的PLL电路。鉴于其简单的拓扑结构,可以使用分立的组件来实现,并且所需的分析最少。因此,所提出的电路非常适合演示本科生实验室中的PLL原理。

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