Low Power And High Speed Sample And Hold For Adc Applications

摘要

This Paper describes the improved design of low voltage sample and hold amplifier for analog to digital converter applications. The proposed design uses double sampling technique to increase the sampling rate, reliable bootstrap switch to reduce switch on resistance and to extend linear range of switch and better SFDR. The designed sample and hold operates at 100MS/s for input signal amplitude of 1.2Vpp.The circuits are designed using CSM 0.18μm technology incadence environment and power consumption estimated was 6.5 mwatt from 1.2V power supply.