2 - High-speed Low-power pipelined ADC utilizing a dynamic reference voltage and 2-stage sample-and-hold

摘要

A fast, low-power pipelined analog-to-digital converter using dynamic reference and two-stage sample and hold is presented. In the pipelined analog-to-digital converter including the plurality of stages proposed in the present invention, each stage includes a two-stage circuit for securing a conversion time corresponding to a clock cycle per stage, A reference voltage generator and a linear transconductor (LT) for receiving the output of the S / H, D-flip flop of the previous stage as an input signal and generating a required reference voltage for half a sampling frequency, a rail- Flip-flop, a reference voltage generator of a next stage for generating an output of the analog-to-digital converter and a reference voltage using the output of the D-flip-flop, And a comparator for generating an input.