FPGA Based Implementation for Ripple Carry Adder with Reduced Area and Low Power Consumption

摘要

A multiplier is one of the key hardware blocks in most digital and high perform ance systems such as FIR filters, digital signal processors and microprocessors etc. With advances in technology, many researchers have tried and are trying to design multipliers which offer either of the follo wing - high speed, low power consumption, regularity of layout and hence less area or even combination of them in multiplier. However area and speed are two conflicting constraints. So improving speed results always in larger areas. So here we try to find out the best trade off solution among the b oth of them. While comparing the adders we found out that Ripple Carry Adder had a smaller area while having lesser speed, in contrast to which Carry Select Adders are high speed but possess a larger area. And a Carry Look Ahead Adder is in between the spectru m having a proper tradeoff between time and area complexities