Negative bias temperature instability (NBTI) is an important lifetime reliability problem in microprocessors. SRAM based structures within the processor are especially susceptible to NBTI since one of the pMOS devices in the memory cell always has an input of ―0‖. Previously proposed recovery techniques for SRAM cel ls aim to balance the degradation of the two pMOS devices by attempting to keep their inputs at a logic ―0‖ exactly 50% of the time. However, one of the devices is always in the negative bias condition at any given time. In this paper, proposed technique called Recovery Boosting that allows both pMOS devices in the memory cell to be put into the recovery mode by slightly modifying to the design of conventional SRAM cells. To evaluate the circuit- level design of a physical register file and an issue queue t hat use such cells through SPICE-level simulations. To conduct an architecture-level evaluatio n of the performance and reliability of using area-neutral designs of these t wo structures. To sho w that Recovery Boosting provides significant improvement in the static noise margins of the register file and issue queue while having very little impact on power consumption and performance
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