A Low Power FIR Filter Design for Image Processing

摘要

In this paper, a new low power design method of the FIR filter for image processing isproposed. Because the correlation between adjacent pixels is very high in image data,the clock gating technique can be a good candidate for low power strategy. However,the conventional clock gating strategy that is applied independently to every flip-flopof the filter give rise to too much additional area overhead and couldn't get a good resultin the power reduction. In our method, each tap register, which is used to delay theinput data in the filter, is partitioned into two sub-registers according to the correlationcharacteristic of its input space. For the sub-register which highly correlated data isinputted into, the dynamic power consumption is reduced by diminishing switchingactivity of the clock signal. We can also reduce the additional hardware overhead bypropagating the clock gating control signal of the first tap register to other tap registers.To identify the efficiency of the proposed design method, we perform the experiments onsome filters that are designed in VHDL. The power estimation tool says that theproposed method can reduce the power dissipation of the filter by more than 18%compared to the conventional filter design methods.