Increased downscaling of CMOS circuits with respect to feature size and threshold voltage has a result ofdramatically increasing in leakage current. So, leakage power reduction is an important design issue foractive and standby modes as long as the technology scaling increased. In this paper, a simultaneous activeand standby energy optimization methodology is proposed for 22 nm sub-threshold CMOS circuits. In thefirst phase, we investigate the dual threshold voltage design for active energy per cycle minimization. Aslack based genetic algorithm is proposed to find the optimal reverse body bias assignment to set of noncriticalpaths gates to ensure low active energy per cycle with the maximum allowable frequency at theoptimal supply voltage. The second phase, determine the optimal reverse body bias that can be applied toall gates for standby power optimization at the optimal supply voltage determined from the first phase.Therefore, there exist two sets of gates and two reverse body bias values for each set. The reverse body biasis switched between these two values in response to the mode of operation. Experimental results areobtained for some ISCAS-85 benchmark circuits such as 74L85, 74283, ALU74181, and 16 bit RCA. Theoptimized circuits show significant energy saving ranged (from 14.5% to 42.28%) and standby powersaving ranged (from 62.8% to 67%).
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