Implementation of 16x16bit and 32x32bit Vedic Multiplier using FPGA board

摘要

This paper proposed the implementation of 16x16bit and 32x32bit Vedic Multiplier using modified Ripple Carry Adder, modified Kogge Stone Adder and BRENT KUNG ADDER on Spartan 6 family xc6slx4 3tqg144 FPGA and its synthesis using XILINX ISE 14.1 simulator