面向低端FPGA的32位硬件乘法器实现

摘要

硬件乘法器广泛应用于数字信号处理，处理速度和硬件资源占用是关心的两个重点。通过使用LPM-ROM宏功能模块，再加以流水线技术的使用和时钟双边沿的数据读取，可以实现速度和资源占用折衷的设计。可应用于信号检测与处理、工业控制等实时控制设计中。%hardware multiplier is widely used in digital system processing, while the processing speed and resources are what is concerned. By implementing LPM-ROM Megafunction as memory to achieve 4＊4 multiplier, using pipelining, and accessing data in both rising edge and falling edge, a compromise can be arrived between high speed and high resources. It can be used in the design of signal detection and processing, industrial control.