FPGA implemented bit-serial multiplier and infinite impulse response

摘要

A bit-serial multiplier and an infinite impulse response filter implemented therewith, both implemented on an FPGA, are described in various embodiments. The bit-serial multiplier includes function generators configured as a multiplicand memory, a multiplier memory, a product memory, a bit-serial multiplier, and a bit-serial adder. The function generators are arranged to perform bit-serial multiplication of values in the multiplier and multiplicand memories.