A Method for Implementing Bit-Serial Finite Impulse Response Digital Filters in FPGAs Using JBits~(TM)

摘要

A method for implementing bit-serial Finite Impulse Response (FIR) filters in Field Programmable Gate Arrays (FPGA) using JBits~(TM) to generate FPGA configuration bitstreams is presented. Traditional general-placement method that uses JBits to generate FPGA configuration bitstreams. The JBits~(TM) based bit-serial FIR filter placement method takes advantage of next-neighbor connectivity of bit-serial arithmetic cores to reduce the length of interconnections between cores and increase packing density of the cores in the FPGA. A design example for a filter with finite-precision coefficients generated by a Peak-Constrained Least-Squares filter design method is presented.