Low power has emerged as a principle theme in t odayelectronic industry. Energy efficiency is one of the most important features of modern electronic systems designed for high speed and port able applications. The power consumption of the electronic devices can be reduced by adoptingdifferent design styles. Adiabatic logic style is said to be an attractive solution for such low power electronic applications.This paper presents an energy efficient technique for digital circuits that uses adiabatic logic. The proposed technique has less power dissipation when compared to the conventio nal CMOS design style. This paper evaluates the full adder in dif ferent adiabatic logic st yles and their results were compared with the conventio nal CMOS design. The simulatio n results indicatethat the proposed technique isadvantageous in many of the low power digital applications.
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