IMPLEMENTATION OF MINUTIAE EXTRACTION USING VERILOG HDL

摘要

Recognition of image signifies the elementary learning of image information. Fingerprint is one of the far most Biometric identification technology used in various application. Designing the hardware for such application is very challenging. This paper focused on designing a modest VLSI architecture for extracting the minutiae components of fingerprint. The architecture is implemented in Verilog and targeted to 0.18 micron Cmos process technology. The design total value is about 1k gate count with the clock speed of 232 MHz. This paper results have shown that efficient hardware architecture.