This work proposes a method used to extract fetal ECG signal. Fetal ECG is used to detect the proper functioning of fetus during the time of labour which helps the clinicians to diagnose the wellbeing of the fetus. In this paper, we used Verilog HDL to design a neural network for extraction of FECG (fetal ECG) from MECG (maternal ECG). XYLINX 3S500 model was used to implement the proposed signal. Fetal ECG was efficiently extracted with the help of an FPGA (field-programmable gate array) kit implementing Verilog HDL software.
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