The applicability of at-speed scan-based logic built-in self-test (BIST ) is being severely challenged by excessive capture power that may cause erroneous test responses even for good circuits. Different from conventional low-power BIST, this paper is the first to explicitly focus on achieving capture power safety with a novel and practical scheme, called capture-power-safe logic BIST (CPS-LBIST ). The basic idea is to identify all possibly-erroneous test responses caused by excessive capture power and use the well-known approach of masking (bit-masking, slice-masking ,vector-masking ) to block them from reaching the multiple-input signature register (MISR ). Experiments with large benchmark circuits and a large industrial circuit demonstrate that CPS-LBIST can achieve capture power safety with negligible impact on test quality and circuit overhead.
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