An Efficacious Runtime Adaptive Hybrid Dram/Pram Memory in FPGA Platform

摘要

Hybrid main memory comprising of DRAM and PRAM becomes quite popular because of theless standby power benefit of PRAM and high performance of DRAM. In this work, theruntime-adaptive control and DRAM bypassing methods are introduced in order to minimizeDRAM refresh energy that occupies a considerable portion of total system power. The work iscarried out by using Xilinx 12.1 simulation tool and the experimental result proves that in theproposed work power consumption is greatly reduced i.e., only requires 3 %, with less areaoverhead while maintaining the speed parameter by comparing with the conventional method .