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A hybrid short read mapping accelerator

机译:混合短读映射加速器

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Background The rapid growth of short read datasets poses a new challenge to the short read mapping problem in terms of sensitivity and execution speed. Existing methods often use a restrictive error model for computing the alignments to improve speed, whereas more flexible error models are generally too slow for large-scale applications. A number of short read mapping software tools have been proposed. However, designs based on hardware are relatively rare. Field programmable gate arrays (FPGAs) have been successfully used in a number of specific application areas, such as the DSP and communications domains due to their outstanding parallel data processing capabilities, making them a competitive platform to solve problems that are “inherently parallel”. Results We present a hybrid system for short read mapping utilizing both FPGA-based hardware and CPU-based software. The computation intensive alignment and the seed generation operations are mapped onto an FPGA. We present a computationally efficient, parallel block-wise alignment structure (Align Core) to approximate the conventional dynamic programming algorithm. The performance is compared to the multi-threaded CPU-based GASSST and BWA software implementations. For single-end alignment, our hybrid system achieves faster processing speed than GASSST (with a similar sensitivity) and BWA (with a higher sensitivity); for pair-end alignment, our design achieves a slightly worse sensitivity than that of BWA but has a higher processing speed. Conclusions This paper shows that our hybrid system can effectively accelerate the mapping of short reads to a reference genome based on the seed-and-extend approach. The performance comparison to the GASSST and BWA software implementations under different conditions shows that our hybrid design achieves a high degree of sensitivity and requires less overall execution time with only modest FPGA resource utilization. Our hybrid system design also shows that the performance bottleneck for the short read mapping problem can be changed from the alignment stage to the seed generation stage, which provides an additional requirement for the future development of short read aligners.
机译:背景技术短期读取数据集的快速增长在敏感性和执行速度方面对短期读取映射问题提出了新的挑战。现有方法通常使用限制性误差模型来计算路线以提高速度,而更灵活的误差模型通常对于大规模应用而言太慢了。已经提出了许多短读映射软件工具。但是,基于硬件的设计相对较少。现场可编程门阵列(FPGA)由于其出色的并行数据处理能力而已成功用于许多特定的应用领域,例如DSP和通信领域,使其成为解决“固有并行”问题的有竞争力的平台。结果我们提出了一种混合系统,该系统使用基于FPGA的硬件和基于CPU的软件进行短读映射。计算密集型对齐和种子生成操作被映射到FPGA。我们提出了一种计算效率高的并行块式对齐结构(Align Core),以逼近传统的动态编程算法。将性能与基于CPU的多线程GASSST和BWA软件实现进行了比较。对于单端对齐,我们的混合系统比GASSST(灵敏度相似)和BWA(灵敏度更高)具有更快的处理速度;对于双端对齐,我们的设计灵敏度比BWA稍差,但处理速度更高。结论本文表明,我们的杂交系统可以基于种子和延伸方法,有效地加速短读序列到参考基因组的映射。在不同条件下与GASSST和BWA软件实施方案的性能比较表明,我们的混合设计实现了高度的敏感性,并且仅需少量的FPGA资源利用即可实现更少的总体执行时间。我们的混合系统设计还显示,可以将短读映射问题的性能瓶颈从对齐阶段更改为种子生成阶段,这对将来短读对齐器的开​​发提出了额外要求。

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