首页> 外文期刊>IEEE Design & Test of Computers Magazine >Advanced fault collapsing (logic circuits testing)
【24h】

Advanced fault collapsing (logic circuits testing)

机译:高级故障崩溃(逻辑电路测试)

获取原文
获取原文并翻译 | 示例
获取外文期刊封面目录资料

摘要

The partitioning of faults into equivalence classes so that only one representative fault per class must be explicitly considered in fault simulation and test generation, called fault collapsing, is addressed. Two types of equivalence, which are relevant to the work reported, are summarized. New theorems on fault equivalence and dominance, forming the basis of an algorithm that collapses all the structurally equivalent faults in a circuit, plus many of the functionally equivalent faults, are presented. Application of the algorithm to a set of benchmark circuits establishes that identification of functionally equivalent faults is feasible, and that, in some cases, they are a large fraction of the faults in a circuit. The collapsing algorithm applies not only to combinational designs but to synchronous sequential circuits as well.
机译:将故障划分为等效类,从而解决故障模拟和测试生成过程中必须明确考虑每个类仅代表一个故障的问题,即故障折叠。总结了与报告的工作相关的两种类型的对等。提出了有关故障等价性和支配性的新定理,构成了使电路中所有结构上等效的故障以及许多功能上等效的故障崩溃的算法的基础。将该算法应用于一组基准电路可以确定功能上等效的故障的识别是可行的,并且在某些情况下,它们是电路故障的很大一部分。折叠算法不仅适用于组合设计,还适用于同步时序电路。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号