Infrastructure for Successful BEOL Yield Ramp, Transfer to Manufacturing, and DFM Characterization at 65 nm and Below

摘要

The challenges presented by deep-submicron interconnect back-end-of-line (BEOL) integration continue to grow in number, complexity, and required resolution at 90 nm and 65 nm. These challenges are causing industrywide delays in technology deployment as well as low and often unstable yields. The historically observed improvements in time to successful yield ramp and final manufacturing yield as the industry deploys new technology nodes disappeared at 90 nm. Such improvements have been significant factors in fueling the semiconductor industry's growth. In this article, we describe an infrastructure developed to specifically address BEOL deep-submicron yield-learning needs. These include the need to reduce the overall time to results and to provide information that manufacturers can successfully use in process and yield debug, and in higher-level design models. This infrastructure establishes a needed foundation for deep submicron technology nodes where design and manufacturing share yield entitlement. By building on this foundation, manufacturers can accelerate yield issue detection and correction, and realize yield-aware design flows.