Tackling Test Challenges for Interposer-Based 2.5-D Integrated Circuits

摘要

2.5-D integrated circuit (IC) is a cost-efficient alternative to through-silicon-via (TSV)-based 3-D IC. In this paper, the authors give a comprehensive summary of the testing challenges of 2.5-D ICs and their existing solutions. They then present a test architecture using e-fuses for prebond interposer testing and a method to reduce power-supply noise during the testing.