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INTEGRATED CIRCUIT ASSEMBLED BY TEST CIRCUIT, INTEGRATED CIRCUIT DEVICE HAVING THE TEST CIRCUIT AND TEST BOARD AND TESTING METHOD FOR THE INTEGRATED CIRCUIT

机译:由测试电路组装的集成电路,具有该测试电路和测试板的集成电路装置以及该集成电路的测试方法

摘要

PROBLEM TO BE SOLVED: To suppress minimum the disadvantage caused by testing such as having too many elements of a test circuit containing in LSI and occurrence of a delay time in the case of testing and LSI with multiple pins using an LSI tester with small number of pins. ;SOLUTION: In the case this device is provided with test circuits 111 to 113 having try-state buffers connected respectively to output terminals in an LSI circuit having 2m output terminals, an LSI 101 containing input buffers 151 and 152 for inputting control signals A and B to the try-state buffers and a test board 102 connecting to m tester pins 1 to m by short-circuiting every two output terminals of the try-state buffers and connecting the input buffers 151 and 152 and tester pins A and B, respectively, the output state of the try- state buffers are changed over in test mode with the control signals A and B. Then, one of output signals 11, 21,...m1 or 12, 22,...m2 of the LSI internal circuit 110 is selected to input in an LSI tester 1-3 and to test.;COPYRIGHT: (C)1998,JPO
机译:要解决的问题:为了最大程度地减少由测试引起的不利影响,例如在LSI中包含过多的测试电路元件以及在测试的情况下出现延迟时间,以及使用数量少的LSI测试仪使用多个引脚的LSI。针脚。 ;解决方案:在此设备上配备测试电路111至113,测试电路的尝试状态缓冲器分别连接至具有2m输出端子的LSI电路的输出端子,LSI 101包含用于输入控制信号A和输入信号的输入缓冲器151和152。 B连接到尝试状态缓冲器和测试板102,该测试板102通过使尝试状态缓冲器的每两个输出端子短路并且分别连接输入缓冲器151和152以及测试器引脚A和B而连接到m个测试器引脚1至m。在测试模式下,使用控制信号A和B切换尝试状态缓冲器的输出状态。然后,LSI的输出信号11、21,... m1或12、22,... m2中的一个选择内部电路110以输入LSI测试器1-3并进行测试。;版权所有:(C)1998,JPO

著录项

  • 公开/公告号JPH10115666A

    专利类型

  • 公开/公告日1998-05-06

    原文格式PDF

  • 申请/专利权人 TOSHIBA CORP;

    申请/专利号JP19960271109

  • 发明设计人 KAWASAKI SOICHI;

    申请日1996-10-14

  • 分类号G01R31/28;G06F11/22;H01L27/04;H01L21/822;

  • 国家 JP

  • 入库时间 2022-08-22 03:02:41

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