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INTEGRATED CIRCUIT ASSEMBLED BY TEST CIRCUIT, INTEGRATED CIRCUIT DEVICE HAVING THE TEST CIRCUIT AND TEST BOARD AND TESTING METHOD FOR THE INTEGRATED CIRCUIT
INTEGRATED CIRCUIT ASSEMBLED BY TEST CIRCUIT, INTEGRATED CIRCUIT DEVICE HAVING THE TEST CIRCUIT AND TEST BOARD AND TESTING METHOD FOR THE INTEGRATED CIRCUIT
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机译:由测试电路组装的集成电路,具有该测试电路和测试板的集成电路装置以及该集成电路的测试方法
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摘要
PROBLEM TO BE SOLVED: To suppress minimum the disadvantage caused by testing such as having too many elements of a test circuit containing in LSI and occurrence of a delay time in the case of testing and LSI with multiple pins using an LSI tester with small number of pins. ;SOLUTION: In the case this device is provided with test circuits 111 to 113 having try-state buffers connected respectively to output terminals in an LSI circuit having 2m output terminals, an LSI 101 containing input buffers 151 and 152 for inputting control signals A and B to the try-state buffers and a test board 102 connecting to m tester pins 1 to m by short-circuiting every two output terminals of the try-state buffers and connecting the input buffers 151 and 152 and tester pins A and B, respectively, the output state of the try- state buffers are changed over in test mode with the control signals A and B. Then, one of output signals 11, 21,...m1 or 12, 22,...m2 of the LSI internal circuit 110 is selected to input in an LSI tester 1-3 and to test.;COPYRIGHT: (C)1998,JPO
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