机译:用于3D-HEVC视差估计的高吞吐量硬件设计
Fed Univ Pelotas UFPel Pelotas RS Brazil;
Fed Univ Pelotas UFPel Pelotas RS Brazil;
Fed Univ Pelotas UFPel Pelotas RS Brazil|Fed Univ Rio Grande Sul UFRGS Porto Alegre RS Brazil;
Fed Univ Pelotas UFPel Pelotas RS Brazil;
Fed Univ Pelotas UFPel Pelotas RS Brazil;
Fed Univ Pelotas UFPel Pelotas RS Brazil;
Fed Univ Pelotas UFPel Pelotas RS Brazil;
Encoding; Hardware; Videos; Three-dimensional displays; Estimation; Redundancy; Standards; 3D-HEVC; Disparity Estimation; Hardware Design;
机译:6WR:硬件友好的3D-HEVC DMM-1算法及其能量感知和高吞吐量设计
机译:3D-HEVC深度地图帧内预测的高吞吐量硬件
机译:可编程图形硬件上的实时联合视差和视差流估计
机译:用于3D-HEVC视差估计的高效,高通量硬件设计
机译:使用基于梯度的视差细化在并行图形硬件上进行稳健的实时立体声匹配
机译:HDL设计的硬件水印保护的设计时间优化
机译:使用迭代细化动态自适应实时视差估计硬件