In this paper, adaptive algorithms for updating the coefficients of an equalizer and a 2-state Viterbi detector for a partial response maximum likelihood (PRML) detector in a digital versatile disc record (DVDR) system are proposed and implemented with field programmable gate array (FPGA). The conventional partial response (PR) equalization method, derived under the conventional minimum mean square error (MMSE) criterion, exhibits performance degradation due to high-frequency noise enhancement effect of the equalizer in the process of compensating the low pass characteristic of an optical channel with an eight-to-fourteen modulation-plus (EFMPlus) coded input. The proposed equalization method achieves performance improvement by effectively equalizing the channel output at the important points, i.e. zero-crossing points, where the information on actual recorded bits is stored. Considering the speed limit of the FPGA chip, the maximum likelihood (ML) detector is implemented by a 2-state Viterbi algorithm which has similar performance to the original 6-state Viterbi detector by selecting an appropriate value for threshold. Following performance analyses of the proposed algorithms for PRML detector by various computer simulation, the PRML detector is implemented by FPGA chip.
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