首页> 外文期刊>IEEE Transactions on Consumer Electronics >VLIW-aware software optimization of AAC decoder on parallel architecture core DSP (PACDSP) processor
【24h】

VLIW-aware software optimization of AAC decoder on parallel architecture core DSP (PACDSP) processor

机译:并行体系结构核心DSP(PACDSP)处理器上AAC解码器的VLIW感知软件优化

获取原文
获取原文并翻译 | 示例

摘要

Audio coding is indispensable in our life and MPEG AAC is one of the most popular audio coding standards. It has been widely used in variant applications. In this paper, we propose VLIW-aware software optimization techniques for the AAC decoding blocks on the parallel architecture core DSP (PACDSP) processor. This approach provides the flexibility for adding new extensions and solves two important issues, low power consumption and limited resources problems on DSP for portable devices. We change the traditional sequential algorithms into parallel processes and minimize the memory utilization of each block. The realized decoder can be operated at a lower frequency of only 15 MHz and needs only 27 Kbytes of program memory and 27 Kbytes of data memory .
机译:音频编码是我们生活中必不可少的,而MPEG AAC是最流行的音频编码标准之一。它已广泛用于各种应用中。在本文中,我们为并行体系结构核心DSP(PACDSP)处理器上的AAC解码块提出了VLIW感知的软件优化技术。这种方法提供了添加新扩展的灵活性,并解决了两个重要问题,即便携式设备DSP上的低功耗和有限资源问题。我们将传统的顺序算法更改为并行处理,并最大程度地减少了每个块的内存利用率。实现的解码器可以在仅15 MHz的较低频率下运行,并且仅需要27 KB的程序存储器和27 KB的数据存储器。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号