Central processing unit with DSP decoder that has X86 cores and DSP cores to map X86 instructions to DSP instructions

摘要

The present invention relates to a central processing unit (CPU) or microprocessor comprising a general purpose CPU component such as an X86 core and a DSP core. The CPU includes an intelligent DSP function decoder or preprocessor that checks the X86 opcode order and determines whether the DSP function is performed. If the DSP function decoder determines that the DSP function is to be performed, the DSP function decoder converts the operation code into a DSP macro instruction provided to the DSP core, or maps the DSP macro instruction. The DSP core executes DSP instructions to execute the desired DSP functions in response to macro instructions. DSP cores improve system performance by performing DSP functions with fewer instructions and reduced clock cycles. When the X86 opcode in the instruction cache or instruction memory does not perform the DSP function, the opcode is transferred to the X86 core as in a conventional computer system. The X86 core and the DSP core are connected to each other, sending and receiving data and timing signals for synchronization purposes. Thus, the DSP core improves system performance by offloading mathematical operations on the X86 core. The DSP core also works simultaneously with the X86 core to provide better performance gains. The present invention generates code that works explicitly in an X86 CPU or CPU according to the present invention, including an X86 core and a DSP core. Therefore, the present invention is compatible with existing software.