Multicore cache hierarchies: design and programmability issues

摘要

Welcome to this special issue of the journal Concurrency and Computation: Practice and Experiencernon Multicore Cache Hierachies - Design and Programmability Issues, which contains three originalrnmanuscripts. Caches have been playing an essential role in the performance of single-core systemsrndue to the gap between processor speed and main memory latency. First level caches are stronglyrnrestricted by their access time but current processors are able to hide most of their latency using outof-rnorder execution as well as miss overlapping techniques. On the other hand, last levels of therncache memory hierarchy are not so dependable on their access time but on their locality issues. Thernlocality in lower levels is filtered by the upper levels. As requests going down in the memoryrnhierarchy, they require a greater number of cycles to be satisfied, so it becomes more difficult tornhide the latency of last-level caches. In multicore systems, their importance is even larger due to therngrowing number of cores that share the bandwidth that this memory can provide. In an attempt tornmake a more efficient usage of their caches, the memory hierarchies of many chip multiprocessorsrnpresent last-level caches, which can be allocated across threads and part of them may be private to arnthread while other parts may be shared by multiple threads. Then, caching techniques will continuerntheir evolution during next years in order to tackle the new challenges imposed by multicorernplatforms and workloads. A clear indicator of the current interest of the research community in newrntechniques for optimizing the performance and power consumption of multicore cache hierarchies isrnthe organization during last years of specific sessions devoted to these topics at top internationalrnconferences on computer architecture and parallel computing.