New system software for parallel programming models on the Intel SCC many-core processor

摘要

Since the beginning of the multicore era, parallel processing has become prevalent across the board. On arntraditional multicore system, a single operating system manages all cores and schedules threads and processesrnamong them, inherently supported by hardware-implemented cache coherence protocols. However,rna further growth of the number of cores per system implies an increasing chip complexity, especially withrnrespect to the cache coherence protocols. Therefore, a very attractive alternative for future many-core systemsrnis to waive the hardware-based cache coherency and to introduce a software-oriented message-passingrnbased architecture instead: a so-called Cluster-on-Chip architecture. Intel’s Single-chip Cloud Computerrn(SCC), a many-core research processor with 48 non-coherent memory-coupled cores, is a very recent examplernfor such a cluster-on-chip architecture. The SCC can be configured to run one operating system instancernper core by partitioning the shared main memory in a strict manner. However, it is also possible to access thernshared main memory in an unsplit and concurrent manner, provided that either the caches are disabled or therncache coherency is then ensured by software. In this article, we detail our experiences gained while developingrnlow-level software for message-passing and shared-memory programming on the SCC. We presentrnan SCC-customized MPI library (called SCC-MPICH) as well as a shared virtual memory system (calledrnMetalSVM) for the SCC. In doing so, we evaluate the potential of both programming models and we showrnhow these models can be improved especially with respect to the SCC’s many-core architecture.