Cache-oblivious matrix algorithms in the age of multicores and many cores

摘要

This article highlights the issue of upcoming wider single-instruction, multiple-data units as well as steadilyrnincreasing core counts on contemporary and future processor architectures.We present the recent port to andrnlatest results of cache-oblivious algorithms and implementations of our TifaMMy code on four architectures:rnSGI’s UltraViolet distributed shared-memory machine, Intel’s latest x86 architecture code-named SandyrnBridge, AMD’s new Bulldozer architecture, and Intel’s future Many Integrated Core architecture. TifaMMy’srnmatrix multiplication and LU decomposition routines have been adapted and tuned with regard to thesernarchitectures. Results are discussed and compared with vendors’ architecture-specific and optimizedrnlibraries, Math Kernel Library and AMD Core Math Library, for both a standard C++ version withrnvectorization compiler switches and TifaMMy’s highly optimized vector intrinsics version. We providerninsights into architectural properties and comment on the feasibility of heterogeneous cores and accelerators,rnnamely graphics processing units. Besides bare-metal performance, the test platforms’ ease of use isrnanalyzed in detail, and the portability of our approach to new and upcoming silicon is discussed with regardrnto required effort on code change abstraction levels.rnAs a result, we demonstrate that because of its generic structure in terms of memory organization,rnTifaMMy executes with equally efficient performance on all four architectures as it automatically adaptsrnitself to architectural parameters without losing performance against the Math Kernel Library and AMDrnCore Math Library, underlining its generic and cache-oblivious properties, as the porting effort was relativelyrnlow compared with that in other implementations.