Exploiting performance, dynamic power and energy scaling in full-system simulators

摘要

Energy consumption constraints have become a critical issue in Multiprocessor Systems on Chip (MPSoC)rndesigns. Whereas processor performance comes with a high power cost, there is an increasing interest inrnexploring the trade-off between power and performance, taking into account the target application domain.rnDynamic Voltage and Frequency Scaling (DVFS) techniques adaptively scale frequency or voltage level ofrnCPU allowing it to reach just enough performance to process the system workload while meeting throughputrnconstraints, and thereby, reducing the energy consumption. To explore this wide design space for energy efficiencyrnand performance, hardware and software components, a system-level simulation infrastructure mustrnprovide features to evaluate power savings mechanisms in early stages of the design. This paper presentsrnan extension work of a framework for MPSoCs designs to support DVFS in MPSoCs simulators and evaluatesrnthree DVFS mechanisms. Our experiments show that applying DVFS in the system can save power andrnenergy consumption, with negligible loss of performance.