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A Modified Partial Product Generator for Redundant Binary Multipliers

机译:冗余二进制乘法器的改进的部分积生成器

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摘要

Due to its high modularity and carry-free addition, a redundant binary (RB) representation can be used when designing high performance multipliers. The conventional RB multiplier requires an additional RB partial product (RBPP) row, because an error-correcting word (ECW) is generated by both the radix-4 Modified Booth encoding (MBE) and the RB encoding. This incurs in an additional RBPP accumulation stage for the MBE multiplier. In this paper, a new RB modified partial product generator (RBMPPG) is proposed; it removes the extra ECW and hence, it saves one RBPP accumulation stage. Therefore, the proposed RBMPPG generates fewer partial product rows than a conventional RB MBE multiplier. Simulation results show that the proposed RBMPPG based designs significantly improve the area and power consumption when the word length of each operand in the multiplier is at least 32 bits; these reductions over previous NB multiplier designs incur in a modest delay increase (approximately 5 percent). The power-delay product can be reduced by up to 59 percent using the proposed RB multipliers when compared with existing RB multipliers.
机译:由于其高模块化和无进位加法,在设计高性能乘法器时可以使用冗余二进制(RB)表示。常规的RB乘法器需要附加的RB部分乘积(RBPP)行,因为通过基数4修改的Booth编码(MBE)和RB编码都生成了纠错字(ECW)。对于MBE乘数,这会导致一个额外的RBPP累积阶段。本文提出了一种新的RB修正的部分乘积发生器(RBMPPG)。它消除了多余的ECW,因此节省了一个RBPP累积阶段。因此,与传统的RB MBE乘法器相比,提出的RBMPPG生成的部分乘积行更少。仿真结果表明,当乘法器中每个操作数的字长至少为32位时,基于RBMPPG的设计可显着改善面积和功耗。与以前的NB乘法器设计相比,这些降低导致适度的延迟增加(大约5%)。与现有的RB乘法器相比,使用建议的RB乘法器可以将功率延迟乘积最多降低59%。

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