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Computation of 2D 8×8 DCT Based on the Loeffler Factorization Using Algebraic Integer Encoding

机译:基于Loeffler因式分解的2D 8×8 DCT的代数整数编码

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This paper proposes a computational method for 2D 8×8 DCT based on algebraic integers. The proposed algorithm is based on the Loeffler 1D DCT algorithm, and it is shown to operate with exact computation—i.e., error-free arithmetic—up to the final reconstruction step (FRS). The proposed algebraic integer architecture maintains error-free computations until an entire block of DCT coefficients having size 8×8 is computed, unlike algorithms in the literature which claim to be error-free but in fact introduce arithmetic errors between the column- and row-wise 1D DCT stages in a 2D DCT operation. Fast algorithms are proposed for the final reconstruction step employing two approaches, namely, the expansion factor and dyadic approximation. A digital architecture is also proposed for a particular FRS algorithm, and is implemented on an FPGA platform for on-chip verification. The FPGA implementation operates at 360 MHz, and is capable of a real-time throughput of$3.6cdot 10^8$2D DCTs of size 8×8 every second, with corresponding pixel rate of$2.3cdot 10^{10}$pixels per second. The digital architecture is synthesized using 180 nm CMOS standard cells and shows a chip area of 7.41 mm$^2$. The CMOS design is predicted to operate at 893 MHz clock frequency, at a dynamic power consumption 13.22 mW/MHz$cdot$V$_{sup}^2$.
机译:提出了一种基于代数整数的2D 8×8 DCT计算方法。所提出的算法基于Loeffler 1D DCT算法,并且显示出可以进行精确的计算(即无差错算术)直至最后的重建步骤(FRS)。所提出的代数整数体系结构保持无差错计算,直到计算出大小为8×8的整个DCT系数块为止,这与文献中声称无差错但实际上在列和行之间引入算术错误的算法不同。明智的2D DCT操作中的1D DCT阶段。针对最终的重建步骤,提出了一种快速算法,采用了两种方法,即扩展因子和二进近似。还针对特定的FRS算法提出了一种数字架构,并在FPGA平台上实现了用于片上验证的数字架构。该FPGA实现以360MHz的频率运行,并且能够实现 n $ 3.6 cdot 10 ^ 8 $ n2D DCT,每秒大小为8×8,相应的像素速率为 n $ 2.3 cdot 10 ^ {10} $ n像素/秒。该数字体系结构是使用180 nm CMOS标准单元合成的,显示的芯片面积为7.41 mm n $ ^ 2 $ n。预计CMOS设计将以893 MHz时钟频率工作,动态功耗为13.22 mW / MHz n $ cdot $ < inline-graphic xlink:href = “ cintra-ieq8-2837755.gif ” /> nV n $ _ {sup} ^ 2 $ n。

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