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机译:基于ADC的串行链路接收器建模,嵌入式和数字均衡
Texas A&M Univ Analog & Mixed Signal Ctr College Stn TX 77843 USA;
Texas A&M Univ Analog & Mixed Signal Ctr College Stn TX 77843 USA|Silicon Labs Austin TX 78727 USA;
Texas A&M Univ Analog & Mixed Signal Ctr College Stn TX 77843 USA|Intel Corp San Jose CA 95134 USA;
Texas A&M Univ Analog & Mixed Signal Ctr College Stn TX 77843 USA;
Texas A&M Univ Analog & Mixed Signal Ctr College Stn TX 77843 USA|Intel Corp Austin TX 78749 USA;
Texas A&M Univ Analog & Mixed Signal Ctr College Stn TX 77843 USA;
Texas A&M Univ Analog & Mixed Signal Ctr College Stn TX 77843 USA;
Analog-to-digital conversion; digital equalization; embedded equalization; high-speed I/O; statistical signaling analysis;
机译:具有嵌入式和数字均衡的基于ADC的串行链路接收器建模
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机译:基于10 Gb / s混合ADC的接收器,具有嵌入式模拟和每个符号动态启用的数字均衡
机译:基于ADC的串行I / O接收器的嵌入式均衡
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机译:基于aDC的串行I / O接收器的嵌入式均衡