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Efficient Realization of Large Size Two's Complement Multipliers Using Embedded Blocks in FPGAs

机译:使用FPGA中的嵌入式模块高效实现大数的2的补数乘法器

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This paper presents an optimized design approach for two's complement large size multipliers using smaller size embedded multiplier blocks available as resources in field programmable gate arrays (FPGAs). The realization is based on the Baugh-Wooley algorithm, which segments the multiplication into unsigned and signed components. To achieve efficient implementation results, a set of optimized schemes for the realization of the additions required for the unsigned multipliers and for combining the unsigned and signed components is proposed. The implementations of the multipliers have been carried out for operands with sizes ranging from 20 to 128 bits. The designs are synthesized and implemented on Xilinx's Spartan-3 in the ISE 8.1 design platform and compared with three other realizations using the following approaches: (1) conventional sign-extension approach, (2) Xilinx's IP-Core generator, and (3) sign-and-magnitude-based approach. The experimental results indicate that our proposed method outperforms the other techniques.
机译:本文提出了一种采用较小尺寸的嵌入式乘法器模块的二进制补码大型乘法器的优化设计方法,该模块可作为现场可编程门阵列(FPGA)中的资源使用。该实现基于Baugh-Wooley算法,该算法将乘法分为无符号和有符号成分。为了获得有效的实现结果,提出了一组优化方案,用于实现无符号乘法器所需的加法以及将无符号和有符号分量进行组合。乘法器的实现是针对大小在20到128位范围内的操作数执行的。这些设计在ISE 8.1设计平台中的Xilinx的Spartan-3上综合并实现,并使用以下方法与其他三种实现方式进行了比较:(1)传统的符号扩展方法;(2)Xilinx的IP内核生成器;以及(3)基于符号和幅度的方法。实验结果表明,我们提出的方法优于其他技术。

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