Multichannel Time Skew Calibration for Time-Interleaved ADCs Using Clock Signal

摘要

Time skew in time-interleaved ADCs (TI-ADCs) degrades the system's linearity significantly.To address this problem, a time skew calibration method is proposed here that employs the divided clock signal as calibration signal. The divided squared clock signal containing a limited number of harmonics is demonstrated to be effective to extract the time skew, which is detected by comparing the estimated mean value of the product of two adjacent channels' signals without extra reference ADC channel. The extracted time skew is subsequently compensated by a capacitor array-based digitally controlled delay block. Simulation results of a 4-channel 1GS/s 12-bit TI-ADC design demonstrated that the proposed calibration technique improved the spurious-free dynamic range of the ADC to 77 dB with a digitally controlled delay block that offers a time tuning resolution of 0.2 ps.