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The VLSI Architecture and Implementation of a Low Complexity and Highly Efficient Configurable SVD Processor for MIMO Communication Systems

机译:用于MIMO通信系统的VLSI架构和实现低复杂性和高效可配置的SVD处理器

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This paper presents the design and implementation of a low complexity and highly efficient configurable singular value decomposition (SVD) processor for 2 x 2, 4 x 4, 6 x 6, and 8 x 8 MIMO wireless communication systems. In order to minimize the area complexity while maintaining comparable throughput, novel data-processing sequences are proposed so that costly matrix multipliers are eliminated. Furthermore, data dependencies are greatly mitigated due to the proposed processing sequences. Therefore, a highly optimized pipelined architecture is designed where the resource utilization and hardware efficiency are significantly improved. Moreover, circuit level optimizations are also applied to further enhance the performance of the proposed SVD processor. The proposed SVD architecture has been implemented with 90 nm technology at 500 MHz clock frequency. The post-layout estimations show that the proposed SVD processor achieves a throughput of 1.1 M matrices/s for 8 x 8 MIMO communication systems with the hardware complexity of 192.2 kilo Gate Equivalents. Compared to the state-of-the-art design that supports 2 x 2, 4 x 4, 6 x 6, and 8 x 8 MIMO configurations, the proposed architecture demonstrates a 46% reduction in area complexity and a 22% improvement in hardware efficiency.
机译:本文介绍了低复杂性和高效可配置的奇异值分解(SVD)处理器的设计和实现,适用于2 x 2,4 x 4,6 x 6和8 x 8 mimo无线通信系统。为了使面积复杂性最小化,同时保持相当的吞吐量,提出了新的数据处理序列,从而消除了昂贵的矩阵乘法器。此外,由于所提出的处理序列,可以大大减轻数据依赖性。因此,设计了高度优化的流水线架构,其中设计了资源利用和硬件效率显着提高。此外,还应用了电路电平优化以进一步增强所提出的SVD处理器的性能。所提出的SVD架构已经以500 MHz时钟频率为90nm技术实现。后布局估计表明,所提出的SVD处理器实现了1.1 M个矩阵的吞吐量,用于8 x 8 MIMO通信系统,其硬件复杂度为192.2千栅等价物。与支持2 x 2,4 x 4,6 x 6和8 x 8 mimo配置的最先进的设计相比,该建议的架构展示了面积复杂度降低46%,硬件改进22%效率。

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