A Novel High Speed, Low Power, and Symmetrical Phase Frequency Detector with Zero Blind Zone and π Phase Difference Detection Ability

摘要

This paper presents a novel symmetrical phase frequency detector (PFD) sensitive to the falling edge of input clocks. Notably, the new PFD has an open-loop structure and no reset path, since UP and DN (outputs of the PFD) are never allowed to reach logic high simultaneously. Hence, the blind zone is completely eliminated in this case. Dead zone has been reduced to a great extent about 68 fs. Meanwhile, the proposed PFD is reliably capable of detecting from 0 degrees to 360 degrees, even 180 degrees phase difference between clocks correctly by itself. The PFD has been simulated using the H-SPICE level 49 of a standard 0.18 mu m CMOS process. It has been simulated in different conditions. Its maximum operating frequency at the worst-case conditions varied from 1.4 to 4.7 GHz at different supply voltages varied from 1.2 to 2.4 V. It can operate from very low frequencies up to 4.3 GHz at the power supply of 1.8 V, reliably. It can be used in high-speed and low-power applications. The new PFD consumes power within a range from 11.79 to 478.8 mu W when operating at 50 MHz and 4.3 GHz, respectively. It has also been simulated in different process corners. Using the minimum size devices leads to a compact layout and die size of about 124.3 mu m(2).