A Novel Multiplexer-Based Quaternary Full Adder in Nanoelectronics

摘要

Using multi-valued logic (MVL) can reduce the chip area and connections which have direct effect on power consumption. Recently, according to the high ability of nanotechnology in designing MVL, some researchers have focused on this advanced approach. In this paper, primarily, a new design of quaternary multiplexer 4:1 with carbon nanotube field-effect transistors (CNFETs) is proposed. Afterward, quaternary successor, quaternary predecessor, and quaternary second level successor (quaternary second level predecessor) cells are, for the first time, introduced based on CNTFETs. All of the above-mentioned designs are applied to quaternary half adder and quaternary full adder circuits. To approve the designs, the performance is simulated by HSPICE simulator for 32-nm technology with the Stanford compact SPICE model for CNFETs. The results of simulation represent the improved PDP by 67.14% compared to the best current techniques in the literature. All of the proposed designs are evaluated under various operation conditions such as drive ability, fabrication tolerance, and different supply voltages, confirming the performance of proposed circuits.