Digital delay locked loop-based frequency synthesiser for Digital Video Broadcasting-Terrestrial receivers

摘要

In this study, the authors cover French very high frequency (VHF) band with a novel all-digital fast lock delayed looked loop (DLL)-based frequency synthesiser. Since this new architecture uses a digital signal processing unit instead of phasefrequency detector, charge pump and loop filter in conventional DLL therefore it shows better jitter performance, locktime and convergence speed. To obtain in-phase input and output signals in DLLs, optimisation methods are used in the proposed architecture. The proposed architecture is designed to cover channels of French VHF band by choosing number of delay cells in signal path. Simulation has been done for 22-27 delay cells and fREF = 16 MHz which can produce output frequency in range of 176-216 MHz. Locking time is approximately 0.5 ;C;s which is equal to 8 clock cycles of reference clock. All of simulation results show superiority of the proposed structure.