Spur reduction architecture for multiphase fractional PLLs

摘要

In this study, a multiphase fractional phase-locked loop (PLL) is presented with methods to reduce spurs. General causes of spurs are non-idealities of the phase-frequency detector (PFD) and charge pump (CP) and phase errors between the adjacent phases from the oscillator. In the architecture, the non-idealities of the PFD and CP are compensated and a phase correction circuit is added after the oscillator phase generator to reduce the phase errors, and hence minimise the spurs. Spurs may still be persistent after these modifications due to process variations and device mismatch. The effect is visible in the perturbations of the loop filter control voltage. The residual spurs are minimised by further filtering the control voltage using a moving average filter and then applying it to the oscillator. The PLL is designed in 180 nm technology and outputs a 400 MHz carrier. The highest fractional spur is decreased from -36 to -66 dBc through phase correction and control voltage filtering.