INTEGER BOUNDARY SPUR MITIGATION FOR FRACTIONAL PLL FREQUENCY SYNTHESIZERS

摘要

A clock generation circuit is disclosed. The clock generation circuit includes a first PLL circuit configured to generate a first output clock based on a first input clock, where the first PLL circuit includes a first feedback divider circuit. The clock generation circuit also includes a second PLL circuit configured to generate a second output clock based on a second input clock, where the second PLL circuit includes a second feedback divider circuit. The first input clock is generated based on the second output clock.